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SMSLS320-02 - FLIP CHIP |
| GOLD CHIP TECHNOLOGY™ | HIGH INPUT IMPEDANCE BiFET AMPLIFIER |
| FEATURES | APPLICATIONS | BiFET Amplifier - FLIP CHIP |
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HIGH INPUT IMPEDANCE rGs = 100GΩ HIGH TRANSCONDUCTANCE YFS = 30mS Low Noise (25uV=typ) Low Capacitance (crss= 1.5pf max) Single Chip - Monolithic Construction Ideal For Low Power/Battery Applications Ideal for Piezo Electric Sensing Applications Direct Replacement for Amperex LTA-320 and Linear Integrated Systems LS320 High reliability Unique new design in 0402 style case Gold metallization RoHS compliant, Lead Free Compatible with both chip and wire, flip chip and surface mount assembly. |
Accelerometer Amplifiers Differential Amplifiers Electrometers Force and Preasure Sensors Hydrophone Amplifier Infrared Amplifiers Quartz and Piezo Ceramic Amplifiers Source Follower Unity Gain Buffer Amplifier High Impedance Sense Amplifier Applications Chip on Board System in package SIP Hybrid Circuits |
 
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| HIGH INPUT IMPEDANCE BiFET AMPLIFIER - PRODUCT DESCRIPTION |
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BiFET or Bipolar Field Effect Transistor as an amplifying device comprises a field effect transistor-bipolar transistor pair.
Such a device combines the main desirable features of both field effect transistors and bipolar transistors, therefore,
having a high input impedance that is typical of FETs and a high transconductance (or high current gain) which is typical
of bipolar transistors. Flip Chip BiFET Amplifiers Integrated Circuits series are available in die form in four different pad compositions: -FC, -GB, -GT and -AN. These products are ideal for high reliability hybrid circuits, multi chip module applications and surface mount applications. |
| HIGH RELIABILITY BARE DIE AND SYSTEM IN PACKAGE - SHORT APPLICATION NOTE |
| COB (Chip on Board) and SiP (System-in-Package) are integrating proven mature products in bare die of mixed technologies i.e. Si, GaAs, GaN, InP, passive components, etc that cannot be easily implemented in SOC (System-on-Chip) technology. COB and SiP have small size footprint, high density, shorter design cycle time, easier to redesign and rework, use simpler and less expensive assembly process. For extreme applications the bare die has to withstand also harsh environmental conditions without the protection of a package. KGD, Known Good Die concept is no longer satisfactory if the die cannot withstand harsh environmental conditions and degrades. Standard semiconductor devices supplied by many manufacturers in bare die are build with exposed aluminum pads that are extremely sensitive to moisture and corrosive components of the atmosphere. Semiconix has reengineered industry standard products and now offers known good die for bare die applications with gold interconnection and well-engineered materials that further enhance the die reliability. Semiconix also offers Silicon Printed Circuit Board technology with integrated passive components as a complete high reliability SIP solution for medical, military and space applications. See AN-SMX-001 |
| DISCRETE SEMICONDUCTORS MANUFACTURING PROCESS |
| Discrete semiconductors are manufactured using Semiconix in house high reliability semiconductor manufacturing processes. All semiconductor devices employ precision doping via ion implantation, silicon nitride junction passivation, platinum silicided contacts and gold interconnect metallization for best performance and reliability. MNOS capacitors, Tantalum Nitride TaN or Sichrome SiCr thin film resistors are easily integrated with discrete semiconductors on same chip to obtain standard and custom complex discrete device solutions. |
| ABSOLUTE MAXIMUM RATINGS @ 25 °C (unless otherwise stated) | |||
| Parameter | Symbol | Value | Unit |
| Maximum Storage Temperature | TSTG | -65 to +150 | °C |
| Maximum Operating Junction Temperature | TJ | -55 to +125 | °C |
| Maximum Continuous Power Dissipation @ +125 °C | PD | 200 | mW |
| Maximum Drain Current | ID | 25 | mA |
| Maximum Voltages Drain to Source1 | VDSO | 20 | V |
| Maximum Voltages Gate to Source | VGSS | 20 | V |
| Electrical Characteristics* TC = 25°C unless otherwise noted | ||||||
| Name | Symbol | Test Conditions | Value | Unit | ||
| Min. | Typ. | Max | ||||
| Drain to Source Voltage | VΔS | IDS= 100µA, VGS= 0V | -20 | V | ||
| Gate to Source Voltage | VGS | IDS= 10mA, Vgs= -10V2,3 | -12 | -10 | -7 | V |
| Common Source Forward Transconductance | gfs | IDS= 10mA, VDS= -10V, f= 1kHz | 30000 | µS | ||
| Common Source Output Conductance | goss | IDS= 10mA, VDS= -10V, f= 1kHz | 300 | µS | ||
| Gate to Source Input Resistance | rGs | VGS= 0 to 20V, TJ to 125 °C | 100 | GΩ | ||
| Input Capacitance | CISS | IDS= 10mA, VDS= -10V | 8 | pF | ||
| Reverse Transfer Capacitance | CRSS | IDS= 10mA, VDS= -10V | 1.5 | pF | ||
| Noise Voltage | en | IDS= 10mA, VDS= -10V, BW= 50 to 15kHz | 25 | µV | ||
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1. Absolute maximum ratings are limiting values above which serviceability may be impaired. 2. The gate to source voltage must never exceed 100V, t<10ms. |
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| SPICE MODEL | ||||||
| Spice model pending. | ||||||
| CROSS REFERENCE PARTS: Amperex LTA-320, Linear Integrated Systems LS320 | ||||||
| GENERAL DIE INFORMATION | ||||||||||||||||||||||||
| Substrate | Thickness [mils] |
Size LxW[mils] |
Bonding pads dimensions per drawing | Backside | ||||||||||||||||||||
| Silicon | 10±2 | 20x40±2 |
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Optional backside coating and/or marking. | ||||||||||||||||||||
| LAYOUT / DIMENSIONS / PAD LOCATIONS | ||||||
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Package pinout: 1 - S, 2 - S, 3 - D, 4 - G, |
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| SEMICONDUCTOR ASSEMBLY PROCESS - SHORT APPLICATION NOTE |
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Semiconix flip chip components are designed for dry assembly processes as well as for processes that use adhesives, fluxes etc. Dry assembly
process is an assembly process that does not use additional solders, fluxes or adhesives. Thermosonic wire bonding is a dry assembly process.
Semiconix Flip Chip -FC series can be also used for thermosonic wire bonding. Semiconix Gold Bump -GB series are flip chips that are thermosonically
attached to a circuit. Semiconix Gold Tin -GT series are flip chips with Au/Sn, 80/20 metallized pads. GT series can be attached to circuits by
bringing the die in contact with a substrate which temperature is more than 280°C. Upon cooling bellow 280C, the die is firmly welded to the
substrate. Flux less dry assembly is most reliable but is also most expensive because of thick gold bumps or expensive Au/Sn process. Semiconix -FC series is designed to be used for flip chip assembly with conductive silver epoxy. It is a simple and inexpensive process consisting of 3 steps: - transfer a thin conductive epoxy layer onto the bonding pads; -align to substrate and attach; -cure silver epoxy and inspect. Same procedure may be used also with -GB series in certain applications. Semiconix Gold/Nickel -AN series is the most efficient wafer level chip size package W-CSP designed for mixed surface mount and flip chip applications. The assembly process is same as for packaged surface mount components. The process consist of at least 3 steps; -screen print solder paste on the printed circuit board; -flip chip, align and attach to the tacky solder paste; -dry paste, reflow at T>220°C, clean, etc. Semiconix Flip Chip -AN series are available in many sizes with landing pads compatible with the industry standard CSP as well as surface mount packages. |
| STANDARD PRODUCTS ORDERING INFORMATION |
| VERSION | SMX P/N | WAFFLE PACKS | QUANTITY | U/P($) | FILM FRAME | MIN QUANTITY | U/P($) |
| Flip chip | SMSLS320-02-FC | -WP | 10000 | -FF | 19000 | ||
| Flip chip | SMSLS320-02-FC | -WP | 50000 | -FF | 95000 | ||
| Gold Bump | SMSLS320-02-GB | -WP | 10000 | -FF | 19000 | ||
| Gold Bump | SMSLS320-02-GB | -WP | 50000 | -FF | 95000 | ||
| Gold-Tin | SMSLS320-02-GT | -WP | 10000 | -FF | 19000 | ||
| Gold-Tin | SMSLS320-02-GT | -WP | 50000 | -FF | 95000 | ||
| Gold/Nickel | SMSLS320-02-AN | -WP | 10000 | -FF | 19000 | ||
| Gold/Nickel | SMSLS320-02-AN | -WP | 50000 | -FF | 95000 |
| PRICES - Listed prices are only for standard products, available from stock. Inventory is periodically updated. List prices for other quantities and tolerances are available on line through Instant Quote. For standard products available from stock, there is a minimum line item order of $550.00. No rights can be derived from pricing information provided on this website. Such information is indicative only, for budgetary use only and subject to change by SEMICONIX SEMICONDUCTOR at any time and without notice. |
| LEAD TIMES - Typical delivery for standard products is 4-6 weeks ARO. For custom devices consult factory for an update on minim orders and lead times. |
| CONTINOUS SUPPLY - Semiconix guarantees continuous supply and availability of any of its standard products provided minimum order quantities are met. |
| CUSTOM PRODUCTS - For custom products sold as tested, bare die or known good die KGD, there will be a minimum order quantity MOQ. Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For high volume and pick and place applications, dice are also shipped on film frame -FF. For special die level KGD requirements, different packaging or custom configurations, contact sales via CONTACTS page. |
| SAMPLES - Samples are available only for customers that have issued firm orders pending qualification of product in a particular application. |
| ORDERING - Semiconix accepts only orders placed on line by registered customers. On line orders are verified, accepted and acknowledged by Semiconix sales department in writing. Accepted orders are non cancelable binding contracts. |
| SHIPING - Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For high volume and pick and place applications, dice are also shipped on film frame -FF. |
| DISCLAIMER - SEMICONIX has made every effort to have this information as accurate as possible. However, no responsibility is assumed by SEMICONIX for its use, nor for any infringements of rights of third parties, which may result from its use. SEMICONIX reserves the right to revise the content or modify its product line without prior notice. SEMICONIX products are not authorized for and should not be used within support systems, which are intended for surgical implants into the body, to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without the specific written consent. |
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